1. Field of the Invention
The invention relates to input/output (I/O) interface circuitry for high speed data communications applications. More specifically the invention relates to low voltage differential signaling (LVDS) drivers, for use in the fields of communications, video and other integrated circuits that demand very high data transfer rates.
2. Description of the Related Art
Differential drivers are well known. Differential drivers are used in many input/output (I/O) applications such as in communications, video and integrated circuits that may demand high data transfer rate. Differential drivers are used in integrated circuits (IC) for on-chip communications between circuits, chip-to-board, off-chip communications, etc.
Low-voltage differential signaling (LVDS) technology was developed in order to provide a low-power and low-voltage alternative to other high-speed I/O interfaces specifically for point-to-point transmissions, such as those used in a network devices within data and communication networks. LVDS drivers can be implemented to overcome some deficiencies with previous I/O interface circuitry. However, the LVDS standard provides strict specifications for signal input and output characteristics, such as common mode voltage, differential voltage, etc.
In conventional I/O designs, high-speed data rates are accomplished with parallel I/O structures, each I/O device typically having a limited bandwidth. As bandwidth increases, more I/O devices are required to achieve the increased bandwidth. Over the years, bandwidth has increased substantially leading to massive parallelism in I/O designs in ICs. As a result, these parallel I/O structures occupy more and more space on ICs. This complicates the design of the circuits because there is less available space on the chip. The use of parallel structures also creates a need for additional supporting power supplies because of the numerous extra pads, current sources, etc. necessary in a parallel structure. Thus, most existing I/O drivers are not power efficient.
In portable devices, such as laptop computers, the power coming from the battery, low power allows for longer operating time. In the case where power is not restricted, such as in a desk top PC, power consumption is also important in IC. For example, if a CPU consumes more power, it will require an expensive package for the IC and possibly an additional cooling fan. Therefore, lower power means lower cost to the system.
A prior art LVDS driver is shown in FIG. 1. The metal oxide silicon (MOS) transistor 100 is represented with a circle at the gate indicating that it is a P-type MOS (PMOS) transistor. Transistors 101, 110, 111, 120 and 121 are N-type (NMOS) transistors. The driver includes two current sources 100 and 101, and four current switching NMOS transistors 110, 111, 120, and 121. PMOS transistor 100 provides current from VDD to the top switching transistors 110 and 121. A bias voltage Vb1 controls the amount of current following through the transistor 100. The bottom NMOS sinks current from the switching transistors 120 and 111 to ground (GND). A second bias, voltage Vb2, controls the current following through the transistor 101. Biasing this circuit is fairly easy, and bias voltages are typically provided using current mirrors.
In normal operation, only one group of switching can be on. In the case when transistors 110 and 111 are ON and 120 and 121 are OFF, the current from the current source 100 flows through the switching transistor 100 and follows to the load resistor 130. A voltage drop develops on the terminal of the resistor 130. Since, in this case, the current follows from bottom node 132 to top node 131, the bottom node 132 has a higher potential than the up node 131. The current on the top node 131 is sunk by current source 101 through the switching transistor 111. The current source 101 should sink the same amount of current as provided by current source 100, to get the common mode voltage correctly.
In the opposite case, when transistors 110 and 111 are OFF and transistors 121 and 121 are ON, current will create a voltage drop of a reversed polarity on the load resistor 130. In this case, the top node 131 has a higher potential than the bottom node 132.
There are two major drawbacks in this circuitry for high speed IC applications. First, operating speed is limited due to the high impedance design. Node Vhigh and node Vlow are high impedance nodes with relatively large parasitic capacitance, and therefore, are slow to respond. In high speed switching, these nodes also cause the common mode voltage to drift. A poorly designed current source, as an example, could have an impedance above a few kilo-ohms. Moreover, a well designed current source will have much higher impedance. Moreover, a well designed current source, such as cascoded current source, will have much high impedance.
Second, in a high speed serial interconnection, termination at the driver side may be required for good signal integrity. This circuit does not include terminal resistors, and therefore, has poor signal integrity at high speeds.
FIG. 2 shows another prior art implementation of an LVDS driver that has built-in termination resistors. The operation of the circuit is very similar to the first circuit, except the load is now shared with the resistors 150 and 151. The impedances at the current source 100 and 101 are very high and can be neglected compared to the termination resistor. To terminate the source properly, resistors 150 and 151 need to be half the resistance of the resistor 130. For a typical application, resistor 130 is 100 ohms. Thus, resistors 150 and 151 need to be 50 ohms each. In this design, the same amount of current will follow into resistors 150 and 151. The advantage of adding resistors 150 and 151 is that the impedance at Vhigh and Vlow are reduced for high speed operation. Also, since this reduces reflection in the transmission line, signal integrity is improved. However, the current efficiency of this driver is 50% because only 50% of the current generated flows to the load. Thus, this circuit design is deficient for having a low current efficiency.
In view of the deficiencies in the prior art, there is a need for new and improved systems and methods for driving LVDS in modern I/O applications.